Design and Analysis of Phased-array Transmitter Building Blocks for mmWave Communications
Project Description
mmWave integrated circuits are extensively utilized in 5G/6G and satellite communication applications to support high-speed data transmission of up to tens of gigabits per second. This field is also a prominent area of research, drawing significant attention and efforts from both industry and academia, including major players like Intel, Qualcomm, and Broadcom.
In this project, students will learn to simulate and optimize an existing phased-array transmitter [1][2], focusing on essential components such as power amplifier (PAs), mixer, and variable-gain amplifier (VGA). Initially, they will explore fundamental concepts and principle of the phased-array transmitter. Then, they will port the existing transmitter building blocks from TSMC 40-nm CMOS to TSMC 28-nm CMOS technology. Further, student will learn and conduct pre- and post-simulations on the ported circuit to ensure the building blocks’ function as intended. This research will conclude with an assessment of the efficiency and performance improvements of the phased-array transmitter circuits after technology porting.
Reference:
[1] Z. Liu, L. Wang, R. Ma, Z. Chen and C. Patrick Yue, "A Compact 28-GHz Transmitter Front End with Co-Optimized Wideband Chip–Antenna Interface," in IEEE Transactions on Microwave Theory and Techniques, Early Access.
[2] L. Wang, Z. Liu, H. Fallah, R. Ma, Z. Chen and C. P. Yue, "A 28-GHz Phased-Array Transmitter Achieving 24% Peak Efficiency, 0.26-mm2/ Element Area Efficiency with Completely Orthogonal Phase and Gain Control," 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, 2024, pp. 496-499.
In this project, students will learn to simulate and optimize an existing phased-array transmitter [1][2], focusing on essential components such as power amplifier (PAs), mixer, and variable-gain amplifier (VGA). Initially, they will explore fundamental concepts and principle of the phased-array transmitter. Then, they will port the existing transmitter building blocks from TSMC 40-nm CMOS to TSMC 28-nm CMOS technology. Further, student will learn and conduct pre- and post-simulations on the ported circuit to ensure the building blocks’ function as intended. This research will conclude with an assessment of the efficiency and performance improvements of the phased-array transmitter circuits after technology porting.
Reference:
[1] Z. Liu, L. Wang, R. Ma, Z. Chen and C. Patrick Yue, "A Compact 28-GHz Transmitter Front End with Co-Optimized Wideband Chip–Antenna Interface," in IEEE Transactions on Microwave Theory and Techniques, Early Access.
[2] L. Wang, Z. Liu, H. Fallah, R. Ma, Z. Chen and C. P. Yue, "A 28-GHz Phased-Array Transmitter Achieving 24% Peak Efficiency, 0.26-mm2/ Element Area Efficiency with Completely Orthogonal Phase and Gain Control," 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, 2024, pp. 496-499.
Supervisor
YUE Chik Patrick
Quota
3
Course type
UROP1100
UROP2100
UROP3100
UROP4100
Applicant's Roles
Eligible students should complete ELEC 3400, 3410, and 3500, and be experienced with Cadence circuit design tools. Students who have taken ELEC 4420 are preferred.
In this project, student will be responsible for migrating one of building blocks of an existing phased-array transmitter from TSMC 40-nm CMOS node to TSMC 28-nm CMOS node, conducting pre- and post-layout simulations on the migrated circuit to assess performance improvement, optimizing the migrated circuit according to simulation results, and taping out the migrated circuit for actual chip if the simulation results are promising.
In this project, student will be responsible for migrating one of building blocks of an existing phased-array transmitter from TSMC 40-nm CMOS node to TSMC 28-nm CMOS node, conducting pre- and post-layout simulations on the migrated circuit to assess performance improvement, optimizing the migrated circuit according to simulation results, and taping out the migrated circuit for actual chip if the simulation results are promising.
Applicant's Learning Objectives
1. Students will enhance their knowledge in high-frequency analog circuit and mmWave communication system.
2. Students will gain complete skill required for designing a practical analog integrated circuit.
3. Students have chance to publish patent and academic papers based on their work.
2. Students will gain complete skill required for designing a practical analog integrated circuit.
3. Students have chance to publish patent and academic papers based on their work.
Complexity of the project
Challenging