Design and analysis of low-power flip flops
Project Description
Understand the working principle as well as the area-delay-power trade-off associated with state-of-the-art nanometer-scale flip flop topologies and (possibly) propose a new lower-power-consuming transistor-level flip flop architecture. Students must have taken ELEC3410.
Supervisor
SARFRAZ, Khawar
Quota
2
Course type
UROP1000
UROP1100
UROP2100
Applicant's Roles
Perform an extensive literature review of state-of-the-art flip flop topologies. Understand the working principle and run simulations to verify operation under process-voltage-temperature fluctuations. Perform layout of selected topologies. Propose a new low-power flip flop circuit.
Applicant's Learning Objectives
Advanced features of the industry-standard Cadence design suite. Setting up correct simulations to verify functionality and performance. Gain insight into the operating principle of flip flop circuits. Appreciate and understand the trade-offs associated with nanometer scale flip flop circuits.
Complexity of the project
Moderate