Investigation of Compact DC–DC Converter Architectures for AI Processor Power Delivery
Project Description
AI processors require high-current, low-voltage power delivery with high efficiency and compact size. Vertical power delivery and near-package voltage regulation are promising solutions, but selecting suitable converter topologies and passive components for 48 V/12 V/6 V-to-1 V conversion remains challenging.
This project will conduct a simulation-based investigation of compact DC–DC converter architectures for AI processor power delivery. The student will build simulation models, compare converter topologies and passive component choices, and evaluate key tradeoffs in efficiency, power density, ripple, device stress, and thermal behavior.
This project will conduct a simulation-based investigation of compact DC–DC converter architectures for AI processor power delivery. The student will build simulation models, compare converter topologies and passive component choices, and evaluate key tradeoffs in efficiency, power density, ripple, device stress, and thermal behavior.
Supervisor
WANG, Ping
Quota
1
Course type
UROP2100
UROP3100
UROP4100
Applicant's Roles
1. Review recent developments in AI processor power delivery, including vertical power delivery, near-package voltage regulation, multiphase converters, hybrid converters, and advanced passive component designs.
2. Build circuit simulation models for selected DC–DC converter topologies targeting 48 V/12 V/6 V-to-1 V conversion, and evaluate their efficiency, voltage/current stress, ripple, and transient behavior.
3. Compare different converter architectures and passive component choices using simulation results, and summarize key design tradeoffs related to efficiency, power density, thermal stress, and implementation complexity.
2. Build circuit simulation models for selected DC–DC converter topologies targeting 48 V/12 V/6 V-to-1 V conversion, and evaluate their efficiency, voltage/current stress, ripple, and transient behavior.
3. Compare different converter architectures and passive component choices using simulation results, and summarize key design tradeoffs related to efficiency, power density, thermal stress, and implementation complexity.
Applicant's Learning Objectives
1. Understand the requirements and challenges of high-current, low-voltage power delivery for AI processors and data-center computing systems.
2. Develop hands-on experience in power converter simulation, topology comparison, passive component evaluation, and loss-mechanism analysis.
3. Gain research experience in simulation-based design exploration, performance benchmarking, and multi-objective evaluation of advanced DC–DC converter architectures.
2. Develop hands-on experience in power converter simulation, topology comparison, passive component evaluation, and loss-mechanism analysis.
3. Gain research experience in simulation-based design exploration, performance benchmarking, and multi-objective evaluation of advanced DC–DC converter architectures.
Complexity of the project
Challenging