Design and Analysis of Multi-phase Clock Generator Building Blocks for Wireline Communications
Project Description
Multiphase clock generator (MCG) is widely adopted in wireline communication systems to support data re-timing, serialization, and de-serialization. Rapid growth of Ethernet standard demands MCG with higher operating frequency, better jitter performance, higher phase accuracy, and lower power consumption.
This project aims to optimize an MCG for next-generation wireline communications, leveraging HKUST's optical wireless lab (OWL) IC design platform, database, and related research papers. This project involves analyzing and verifying the existing MCG building blocks (phase detector, charge pump, frequency detector, and ring-current-controlled oscillator) in TSMC 40-nm CMOS node [1], followed by porting these circuits to TSMC 28-nm CMOS node and comparing pre-/post-layout simulations to ensure the building blocks’ function as intended. This research will conclude with an assessment of performance improvements of the MCG circuits after technology porting.
Reference:
[1] Z. Zhang, G. Zhu, C. Wang, L. Wang and C. P. Yue, "A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator," IEEE Journal of Solid-State Circuits, vol. 55, no. 10, pp. 2734-2746, Oct. 2020.
This project aims to optimize an MCG for next-generation wireline communications, leveraging HKUST's optical wireless lab (OWL) IC design platform, database, and related research papers. This project involves analyzing and verifying the existing MCG building blocks (phase detector, charge pump, frequency detector, and ring-current-controlled oscillator) in TSMC 40-nm CMOS node [1], followed by porting these circuits to TSMC 28-nm CMOS node and comparing pre-/post-layout simulations to ensure the building blocks’ function as intended. This research will conclude with an assessment of performance improvements of the MCG circuits after technology porting.
Reference:
[1] Z. Zhang, G. Zhu, C. Wang, L. Wang and C. P. Yue, "A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator," IEEE Journal of Solid-State Circuits, vol. 55, no. 10, pp. 2734-2746, Oct. 2020.
Supervisor
YUE Chik Patrick
Quota
3
Course type
UROP1100
UROP2100
UROP3100
UROP4100
Applicant's Roles
Eligible students should complete ELEC 3400, 3410, and 3500, and be experienced with Cadence circuit design tools. Students who have taken ELEC 4420 are preferred.
In this project, student will be responsible for migrating one of building blocks of an existing multi-phase clock generator from TSMC 40-nm CMOS node to TSMC 28-nm CMOS node, conducting pre- and post-layout simulations on the migrated circuit to assess performance improvement, optimizing the migrated circuit according to simulation results, and taping out the migrated circuit for actual chip if the simulation results are promising.
In this project, student will be responsible for migrating one of building blocks of an existing multi-phase clock generator from TSMC 40-nm CMOS node to TSMC 28-nm CMOS node, conducting pre- and post-layout simulations on the migrated circuit to assess performance improvement, optimizing the migrated circuit according to simulation results, and taping out the migrated circuit for actual chip if the simulation results are promising.
Applicant's Learning Objectives
1. Students will enhance their knowledge in high-speed analog circuit and wireline communication system.
2. Students will gain complete skill required for designing a practical analog integrated circuit.
3. Students have chance to publish patent and academic papers based on their work.
2. Students will gain complete skill required for designing a practical analog integrated circuit.
3. Students have chance to publish patent and academic papers based on their work.
Complexity of the project
Challenging