Design and Analysis of VCSEL Transmitter Building Blocks for Optical Communications
Project Description
Vertical-cavity surface-emitting laser (VCSEL)-based interconnects are extensively utilized in data centers to support short-reach optical communications. To address VCSELs’ imperfections which degrade generated high-speed optical signals, transmitter integrated circuit with compensation function is highly demanded. This project aims to optimize an existing VCSEL transmitter integrated circuit (IC) for next-generation optical communications, leveraging HKUST's optical wireless lab (OWL) IC design platform, database, and related research papers.
In this project, student will firstly learn about the concept of VCSEL-based optical communication system and principle of the existing VCSEL transmitter. Then, students will analyze and verify the existing transmitter building blocks, including 4-to-1 multiplexer, clock tree, and output driver, which have been implemented in TSMC 40-nm CMOS node [1]. Following that, student will port these circuits to TSMC 28-nm CMOS node and conduct pre-/post-layout simulations to ensure the building blocks’ function as intended. This research will conclude with an assessment of the efficiency and performance improvements of the transmitter circuits after technology porting.
Reference:
[1] F. Chen, C. Zhang, L. Wang, Q. Pan and C. P. Yue, " A 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Compensation Scheme in 40-nm CMOS," IEEE Journal of Solid-State Circuits, Early Access.
In this project, student will firstly learn about the concept of VCSEL-based optical communication system and principle of the existing VCSEL transmitter. Then, students will analyze and verify the existing transmitter building blocks, including 4-to-1 multiplexer, clock tree, and output driver, which have been implemented in TSMC 40-nm CMOS node [1]. Following that, student will port these circuits to TSMC 28-nm CMOS node and conduct pre-/post-layout simulations to ensure the building blocks’ function as intended. This research will conclude with an assessment of the efficiency and performance improvements of the transmitter circuits after technology porting.
Reference:
[1] F. Chen, C. Zhang, L. Wang, Q. Pan and C. P. Yue, " A 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Compensation Scheme in 40-nm CMOS," IEEE Journal of Solid-State Circuits, Early Access.
Supervisor
YUE Chik Patrick
Quota
3
Course type
UROP1100
UROP2100
UROP3100
UROP4100
Applicant's Roles
Eligible students should complete ELEC 3400, 3410, and 3500, and be experienced with Cadence circuit design tools. Students who have taken ELEC 4420 are preferred.
In this project, student will be responsible for migrating one of building blocks of an existing transmitter IC from TSMC 40-nm CMOS node to TSMC 28-nm CMOS node, conducting pre- and post-layout simulations on the migrated circuit to assess performance improvement, optimizing the migrated circuit according to simulation results, and taping out the migrated circuit for actual chip if the simulation results are promising.
In this project, student will be responsible for migrating one of building blocks of an existing transmitter IC from TSMC 40-nm CMOS node to TSMC 28-nm CMOS node, conducting pre- and post-layout simulations on the migrated circuit to assess performance improvement, optimizing the migrated circuit according to simulation results, and taping out the migrated circuit for actual chip if the simulation results are promising.
Applicant's Learning Objectives
1. Students will enhance their knowledge in high-speed analog circuit and optical communication system.
2. Students will gain complete skill required for designing a practical analog integrated circuit.
3. Students have chance to publish patent and academic papers based on their work.
2. Students will gain complete skill required for designing a practical analog integrated circuit.
3. Students have chance to publish patent and academic papers based on their work.
Complexity of the project
Challenging