Investigating Domain-Specific Hardware Acceleration with Reconfigurable Dataflow Accelerators (RDAs)
Project Description
Reconfigurable Dataflow Accelerators (RDAs) strike a balance between flexibility and high performance, positioning them as a potential solution for the post-Moore era of computation. This project aims to explore the design of domain-specific RDAs. Students will be tasked with designing and evaluating RDA hardware acceleration implementations for specific domains like machine learning and image processing. This work will contribute directly to the development of next-generation computing solutions.
Supervisor
ZHANG Wei
Quota
2
Course type
UROP1100
Applicant's Roles
1) Conduct literature reviews on recent RDA advancements
2) Assist in designing and implementing algorithms for domain-specific acceleration
3) Evaluate and analyze the outcomes of hardware acceleration
2) Assist in designing and implementing algorithms for domain-specific acceleration
3) Evaluate and analyze the outcomes of hardware acceleration
Applicant's Learning Objectives
1) Study fundamental knowledge in hardware acceleration, such as compiler principles, compilation frameworks, etc.
2) Gain practical experience in analyzing hardware acceleration methodologies
3) Understand the trends and frontiers of modern reconfigurable computing technologies
2) Gain practical experience in analyzing hardware acceleration methodologies
3) Understand the trends and frontiers of modern reconfigurable computing technologies
Complexity of the project
Moderate