Using Large Language Model (LLM) to Assist Digital Circuit Design
Project Description
In recent years, large language models (LLMs) such as GPT have demonstrated remarkable performance in natural language processing (NLP). Inspired by this progress, researchers have also started exploring the adoption of LLMs in agile hardware design. A promising direction that perhaps attracts the most attention is automatically generating design RTL based on natural language instructions. Specifically, given design functionality descriptions in
natural language, LLM can directly generate corresponding hardware description language (HDL) code such as Verilog, VHDL, and Chisel from scratch. This LLM-based design generation technique can potentially revolutionize the existing HDL-based VLSI design process, relieving designers from the tedious HDL coding tasks.
In this project, you will get familiar with the aforementioned technique, i.e., Using LLM to Assist Digital Circuit Design. Specifically, you will help read relevant literature and help generate benchmarks that comprehensively evaluate different LLM solutions. You will help explore relevant prompt engineering techniques. Please refer to the "Applicant Roles" for more details.
Please refer to [1] for more background.
[1] Shang Liu, et al., “RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
natural language, LLM can directly generate corresponding hardware description language (HDL) code such as Verilog, VHDL, and Chisel from scratch. This LLM-based design generation technique can potentially revolutionize the existing HDL-based VLSI design process, relieving designers from the tedious HDL coding tasks.
In this project, you will get familiar with the aforementioned technique, i.e., Using LLM to Assist Digital Circuit Design. Specifically, you will help read relevant literature and help generate benchmarks that comprehensively evaluate different LLM solutions. You will help explore relevant prompt engineering techniques. Please refer to the "Applicant Roles" for more details.
Please refer to [1] for more background.
[1] Shang Liu, et al., “RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
Supervisor
XIE Zhiyao
Quota
1
Course type
UROP1100
UROP2100
UROP3100
UROP4100
Applicant's Roles
- Read relevant literature about LLM-assisted circuit design.
- Help generate benchmarks on LLM-assisted circuit design generation. Write circuit designs (e.g., in Verilog), test cases, and design explanations in natural language.
- Help explore prompt engineering techniques that control LLM to generate circuit designs.
- Potential roles: help fine-tune new LLMs in Python; help write a survey paper in this direction. You will work together with our PhD student.
- Help generate benchmarks on LLM-assisted circuit design generation. Write circuit designs (e.g., in Verilog), test cases, and design explanations in natural language.
- Help explore prompt engineering techniques that control LLM to generate circuit designs.
- Potential roles: help fine-tune new LLMs in Python; help write a survey paper in this direction. You will work together with our PhD student.
Applicant's Learning Objectives
- Get familiar with LLM techniques.
- Get familiar with basic digital design methods.
- Learn to read (and possibly write) literature.
- Get familiar with basic digital design methods.
- Learn to read (and possibly write) literature.
Complexity of the project
Challenging