In recent years, large language models (LLMs) such as GPT have demonstrated remarkable performance in natural language processing (NLP). Inspired by this progress, researchers have also started exploring the adoption of LLMs in agile hardware design. A promising direction that perhaps attracts the most attention is automatically generating design RTL based on natural language instructions. Specifically, given design functionality descriptions in natural language, LLMs can directly generate corresponding hardware description language (HDL) code such as Verilog, VHDL, and Chisel from scratch. This LLM-based design generation technique can potentially revolutionize the existing HDL-based VLSI design process, relieving designers from the tedious HDL coding tasks.

In this project, you will get familiar with the aforementioned technique, i.e., using LLMs to Assist Digital Circuit Design. Specifically, you will help read relevant literature and help generate benchmarks that comprehensively evaluate different LLM solutions. You will help explore relevant prompt engineering techniques. Please refer to the "Applicant Roles" for more details.

Please refer to [1] for more background.

[1] Shang Liu, et al., “RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.